The Intel IA32 processors have a base pointer..

software | Windows |

The Intel IA32 processors have a base pointer register called EBP . The
EBP register is typically set to the value of the ESP register at the
 beginning of a procedure, and used to address the procedure arguments
 and locally allocated variables throughout the procedure. Thus, the
 arguments are located at positive offsets from the EBP register, while the
 variables are located at negative offsets from the EBP register.

source :

software | GNU/Linux |

(gdb) info registers
rax            0xfffffffffffffdfc	-516
rbx            0x5dc	1500
rcx            0xffffffffffffffff	-1
rdx            0x5dc	1500
rsi            0x1	1
rdi            0x7ffffb2814d0	140737407096016
rbp            0x1f70160	0x1f70160
rsp            0x7ffffb281480	0x7ffffb281480
r8             0x0	0
r9             0xffffffff	4294967295
r10            0x8	8
r11            0x246	582
r12            0x7ffffb2814d0	140737407096016
r13            0x7ffffb2814e0	140737407096032
r14            0x0	0
r15            0x1	1
rip            0x7f668b3710c8	0x7f668b3710c8
eflags         0x246	[ PF ZF IF ]
cs             0x33	51
ss             0x2b	43
ds             0x0	0
es             0x0	0
fs             0x0	0
gs             0x0	0

rbp 0x1f70160 0x1f70160

In computer architecture, a processor register (or general purpose
 register) is a small amount of storage available on the CPU whose
 contents can be accessed more quickly than storage available
source :

The AMD64 architecture has sixteen 64-bit general purpose registers
 (GPRs): RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, R8, R9, R10, R11, R12,
 R13, R14, and R15. Compared to the x86 architecture, the AMD64
 architecture has eight new GPRs.

source :

| Related Discussion |

 Hi, Could somebody please explain what GCC is doing for this piece of code? What is it initializing? The original code is:

int main()

And it was translated to:

    .file       "test1.c"
    .def        ___main;        .scl    2;      .type   32;     .endef
.globl _main
    .def        _main;  .scl    2;      .type   32;     .endef
    pushl       %ebp
    movl        %esp, %ebp
    subl        $8, %esp
    andl        $-16, %esp
    movl        $0, %eax
    addl        $15, %eax
    addl        $15, %eax
    shrl        $4, %eax
    sall        $4, %eax
    movl        %eax, -4(%ebp)
    movl        -4(%ebp), %eax
    call        __alloca
    call        ___main

| Variation |

Registers E(SP), E(IP) and E(BP) are promoted to 64-bits and are re-named RSP, RIP, and RBP respectively.

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